With development of the semiconductor technology, the feature size of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is continuously reduced. The reduction of the size of the MOSFET may lead to a problem of current leakage. The use of a high-k dielectric enables to increase the physical thickness of the gate dielectric while keeping the equivalent oxide thickness (EOT) invariable, thereby to decrease the gate tunneling leakage current. However, the conventional poly-silicon gate is incompatible with the high-k dielectric. The use of the metal gate and the high-K dielectric together may not only avoid the depletion effect of the poly-silicon gate and reduce the gate resistance, but also may avoid penetration of boron to improve the reliability of the device. Thus, the combination of the metal gate and the high-K dielectric are widely applied in MOSFET. There are still many challenges in the integration of the metal gate with the high-K dielectric, such as thermal stability and interface state. Especially because of the Fermi Pinning effect, it is difficult for the MOSFET employing the metal gate and the high-K dielectric to obtain an appropriately low threshold voltage.
In a CMOS application integrating N type and P type MOSFETs, in order to obtain an appropriate threshold voltage, an effective work function of an NMOSFET should be near a bottom of a conduction band of Si, i.e. about 4.1 eV, and an effective work function of a PMOSFET should be near a top of a valence band of Si, i.e. about 5.2 eV. Thus, difference combinations of metal gates and high-K dielectrics may be selected for the NMOSFET and the PMOSFET respectively to implement the desired threshold voltage. As a result, it would therefore be desirable to provide the integration implementation of double metal gates and double high-K dielectrics on one chip. During manufacturing the semiconductor device, the respective photolithography and etching steps are performed for the metal gate and high-K gate dielectric for NMOSFET and PMOSFET, respectively. Thus, the method for manufacturing a semiconductor device comprising double metal gates and double high-K dielectrics are complex and is not suitable for mass production, which may further increase the manufacturing cost.